The present disclosure relates to a semiconductor structure, and particularly to a dynamic random access memory (DRAM) cell including a finFET access transistor and a method of manufacturing the same.
Deep trench capacitors are used in a variety of semiconductor chips for high areal capacitance and low device leakage. Typically, a deep trench capacitor provides a capacitance in the range from 4 fF (femto-Farad) to 120 fF. A deep trench capacitor may be employed as a charge storage unit in a dynamic random access memory (DRAM), which may be provided as a stand-alone semiconductor chip, or may be embedded in a system-on-chip (SoC) semiconductor chip. A deep trench capacitor may also be employed in a variety of circuit applications such as a charge pump or a capacitive analog component in a radio-frequency (RF) circuit.
As dimensions of semiconductor devices scale, providing a robust low resistance path for electrical conduction between an inner electrode of a transistor and the source of an access transistor becomes a challenge because available area for forming a conductive strap structure decreases. However, because the read time and the write time of a DRAM cell is proportional to the product of the capacitance of a capacitor in the DRAM cell and the resistance of an electrically conductive path connected to the capacitor, a low resistance conductive path between the capacitor and the access transistor is required in order to reduce the read time and the write time of the DRAM cell.